SNPS

Synopsys lives on the workstations of every chip designer at NVIDIA, AMD, Broadcom, Google, Amazon, and every other company building silicon. A chip begins as a behavioral description in a hardware language like Verilog. Synopsys Design Compiler synthesizes that description into actual logic gates. IC Compiler places those gates on the die and routes the connections between them. PrimeTime — the gold standard, used on virtually every commercial tape-out — verifies that all signals arrive within a clock cycle across billions of transistors. StarRC extracts parasitic electrical effects. Only after all of these tools sign off does the design go to TSMC for manufacturing.

The company completed its $35B acquisition of Ansys in January 2025, the largest deal in EDA history. Ansys brings multi-physics simulation — thermal analysis, electromagnetic modeling, structural simulation — capabilities that are increasingly critical as AI accelerators push past 700W power envelopes and chiplet architectures require sub-picosecond timing between dies. The first joint Synopsys-Ansys solutions are expected in H1 2026, with meaningful revenue synergies targeted by FY2027. Management is tracking toward $400M in revenue synergies by year four.

Q1 FY2026 revenue hit $2.41B, with Design Automation contributing roughly $2B and Design IP adding $407M. The company holds $11.3B in backlog — more than a full year of revenue committed — and generated $822M in free cash flow in the quarter. Non-GAAP operating margin was 42.1%. The balance sheet carries $10B in debt from the Ansys financing, but the term loan has been fully repaid and the board authorized a $2B share buyback, signaling confidence in cash generation.

Synopsys divested its ARC processor business to GlobalFoundries to sharpen focus on the higher-margin EDA and simulation platform. China exposure remains a geopolitical overhang — US export controls already restrict certain tool sales, and further tightening would shrink the addressable market by an estimated 15–25%.