Design the Chip

Every chip that will power AI for the next decade begins here — inside EDA software tools that translate logic into physical transistor layouts. Synopsys and Cadence hold a global duopoly that is functionally unbreakable. The barriers are not capital but accumulated engineering: 40 years of algorithms for place-and-route, timing closure, and physical verification at 3nm and below.

The Custom Silicon Surge trend runs directly through this layer. As Amazon (Trainium), Google (TPU), Microsoft (Maia), and Meta (MTIA) race to design their own AI accelerators, EDA license revenue accelerates regardless of which chip wins. Every custom ASIC needs the same design tools. This is the classic picks-and-shovels position — EDA vendors profit from the diversity of design starts, not from backing any single architecture.

What makes L01 structurally interesting is that the bottleneck isn't supply — Synopsys and Cadence can scale software licenses — it's the scarcity of experienced chip designers. The world has perhaps 10,000 engineers who can tape out a competitive 3nm AI accelerator. They're concentrated at NVIDIA, AMD, Broadcom, and the hyperscaler custom silicon teams. The human capital constraint means that even unlimited EDA licenses don't translate to unlimited chip variety. The industry will produce more ASICs than in 2020 but far fewer than the funding environment suggests.

ARM Holdings sits at the intersection of EDA and Custom Silicon — providing the instruction set architecture (ISA) and IP blocks that most custom ASIC teams start with, collecting royalties per chip shipped. If Custom Silicon Surge plays out, ARM's royalty stream diversifies beyond smartphones into AI accelerators at scale.