Package the Chip

This is the most constrained layer in the entire AI supply chain today. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging is the only proven path for integrating GPU dies with HBM memory at the scale NVIDIA needs. CoWoS-L capacity is sold out through 2027, and the materials supply chain feeding it — ABF substrate film from Ajinomoto (monopoly), photomask blanks from HOYA (~70% share), silicon interposer wafers from Shin-Etsu — creates a cascading constraint where bottlenecks multiply.

The Packaging Bottleneck trend IS this layer. Every major AI chip (B200, B300, MI300X, Trainium) requires advanced packaging. The techniques differ — TSMC uses CoWoS, Intel uses EMIB/Foveros, AMD relies on TSMC plus its own chiplet architecture — but they all converge on the same fundamental challenge: putting more compute in less space while feeding it enough data bandwidth.

BE Semiconductor (BESI) makes the hybrid bonding equipment that enables die-to-die connections without solder bumps. This is the next-generation packaging technology that will eventually supplement CoWoS. Kulicke & Soffa provides the wire and ball bonding that handles the simpler packaging steps. Amkor and ASE Technology are the OSATs (Outsourced Semiconductor Assembly and Test) that handle the volume packaging work TSMC doesn't do internally.

The structural insight: packaging is where Moore's Law went when traditional transistor scaling slowed. Instead of making transistors smaller, the industry is making packages larger and more complex — stacking more dies, connecting them with wider buses, and integrating heterogeneous chiplets. This is a permanent architectural shift, not a cyclical demand spike.