The Great Packaging Bottleneck

Modern AI chips are not single pieces of silicon. An NVIDIA Blackwell package contains two GPU dies and eight HBM memory stacks mounted together on a silicon interposer roughly the size of a dinner plate. That integration process — positioning each die within microns of precision, routing thousands of connections between them, sealing the whole assembly — is called advanced packaging. TSMC's version is called CoWoS (Chip-on-Wafer-on-Substrate), and it is the single tightest supply constraint in the AI semiconductor stack.

TSMC produced roughly 35,000 CoWoS wafers per month in late 2024. The target for end of 2026 is 130,000 per month, backed by $56 billion in capital expenditure. Even with that fourfold expansion, the line remains oversubscribed through 2027. NVIDIA's Rubin architecture, scheduled for second-half 2026, demands CoWoS-L (which uses local silicon interconnect bridges to stitch more chiplets together). Rubin Ultra — the Kyber NVL576 rack arriving in 2027 — integrates 576 compute chiplets per rack, each requiring its own substrate work.

Supply is concentrated. No OSAT (outsourced assembly and test) can match TSMC's yield at the leading packaging nodes. ASE, Amkor, and SPIL are taking overflow for earlier-generation packaging. Intel is pushing its own EMIB and Foveros packaging as a CoWoS alternative but remains a distant second for AI-class volume.

Two adjacent shifts compound the constraint. First, TSMC's 2nm N2 node entered volume production in Q4 2025 — the first gate-all-around (GAA) implementation, replacing FinFET. Capacity must ramp from 50,000 to 140,000 wafers per month by December 2026 to meet existing commitments. Every major AI chip from 2026 onward targets this node. Second, the industry is transitioning from organic resin substrates to glass. Intel is targeting mass production in 2026 (40% faster signal speed, 30% lower power, 60% lower dielectric loss). Samsung targets 2028. Glass substrates directly reduce the energy cost of linking HBM memory to compute chiplets — today's single biggest source of wasted power in a modern GPU.

Think of a modern AI chip as a restaurant that needs ingredients from all over the building arriving at exactly the right moment. The "chef" is the GPU. The "ingredients" are the memory stacks. For the chef to cook fast enough, those ingredients need to sit inches away — not in a warehouse across town. The only way to do that is to glue the chef and the ingredients onto one shared countertop so everything is within reach.

That countertop is what advanced packaging builds. It's a piece of precision silicon about the size of a dinner plate, with microscopic wires running through it that connect the GPU to its memory stacks. Positioning everything on that countertop is extraordinarily hard — you're working with tolerances measured in the width of a few atoms. And there is exactly one company in the world that does this at AI-industry scale: TSMC in Taiwan. Their version of the countertop is called CoWoS.

Here's the punchline: the chips themselves are not the bottleneck. TSMC can make plenty of GPU dies. The bottleneck is the countertop factory. TSMC is spending $56 billion to expand that factory — quadrupling capacity by late 2026 — and it is still not enough. Every NVIDIA earnings call, every AMD chip announcement, every Google TPU launch is secretly a conversation about whether TSMC can build countertops fast enough.

And it gets harder before it gets easier. The next generation of racks, Rubin Ultra, will pack 576 compute chiplets into a single rack — each one needing its own slice of countertop. On top of that, the industry is simultaneously switching from a silicon countertop to a glass one (faster, cooler) and moving every chip onto a brand-new transistor design called gate-all-around. All three transitions — more countertops, glass countertops, and new transistors — are happening at once in 2026. That's why "packaging" is where the real scarcity lives, not on the chip itself.