TOELY
Tokyo Electron (OTC)
Summary
What they do:
Build the machines that coat, develop, etch, and deposit thin films on semiconductor wafers — the core process steps in every fab on Earth. TEL holds ~92% global share in coater/developer (the lithography track system), ~38% in dry etch, ~37% in CVD, and ~38% in ALD. Primary listing is Tokyo Stock Exchange (8035.T); TOELY is the OTC ADR.
Why they matter:
Every leading-edge chip — whether TSMC's N3/N2 for NVIDIA, Samsung's gate-all-around logic, or SK Hynix's HBM4 DRAM — requires TEL equipment at multiple process steps. The coater/developer is the only tool that interfaces directly with ASML's EUV scanner; TEL's ~92% share there makes it a de facto sole source for the most critical lithography handoff in the industry.
Recent performance:
FY2025 (ended March 2025) was a record year: revenue JPY 2.43 trillion (~$15.7B), up 32.8% YoY. FY2026 full-year guidance revised to JPY 2,380-2,410B with operating margin ~24.6%. Q3 FY2026 (Oct-Dec 2025) revenue JPY 552B was soft sequentially, but H2 FY2026 is guided to a record half-year at JPY 1,100B+ as AI-driven fab investment accelerates.
Our Verdict
Dominant equipment franchise with ~92% coater/developer share and broad etch/deposition exposure to every major fab buildout — structural AI beneficiary trading at ~35x earnings, fully priced for the current cycle but essential to own through the next decade of fab expansion.
Structural trends
Structural
80
/ 100
Moat
7/10
Top 3-5 globally in coater/developer and etch, sole-source for some process steps
AI Exp.AI Exposure
High~30% AI
Play Type
EstablishedAI Growth
~20%
Rel. Value
100
COMPELLINGPriceLIVE
$140.34
+2.92%
Live via Yahoo Finance · refreshes every 5 min
Market Cap
$127.7B
P/E Ratio
36.9
P/S Ratio
0.1x
52W High
$152.09
52W Low
$66.10
52W Chg
112.3%
Beta
1.32
Tokyo Electron is the largest semiconductor equipment maker in Japan and the third largest globally behind Applied Materials and ASML. Founded in 1963, the company supplies the tools that perform the most critical wafer fabrication steps: coating photoresist onto wafers and developing exposed patterns (coater/developer), removing material with plasma (dry etch), and depositing thin atomic layers of metal and dielectric (CVD and ALD). These are not peripheral tools. They sit at the center of every fab's process flow, and a modern leading-edge wafer passes through TEL equipment dozens of times before it is finished.
The coater/developer franchise is the crown jewel. TEL's CLEAN TRACK lithography track systems hold roughly 92% of the global market. Every EUV lithography step — the most expensive and technically demanding process in chipmaking — requires a coater/developer to apply photoresist before exposure and develop the pattern afterward. ASML makes the scanner; TEL makes the tool that feeds it and catches the output. This near-monopoly position in the EUV track segment means TEL is present in every leading-edge logic and DRAM fab that TSMC, Samsung, Intel, and SK Hynix operate. In etch, CVD, and ALD, TEL competes head-to-head with Applied Materials and Lam Research, holding roughly 37-38% share in each — not dominant, but large enough to win Process of Record positions on critical layers at major customers.
FY2025 (April 2024 through March 2025) was a record year. Revenue reached JPY 2.43 trillion (~$15.7B), up 32.8%, driven by surging DRAM investment — particularly HBM for AI — and sustained leading-edge logic spending at TSMC and Samsung. Operating profit hit JPY 697B with a 28.7% operating margin. China accounted for roughly 34-38% of revenue, though this share declined from the prior year peak of ~47% as TEL rebalanced toward Taiwan (~20%), Korea (~18%), and a growing North America segment (~15%) supported by CHIPS Act-funded fabs.
FY2026 has been a transition year. Q1 (Apr-Jun 2025) and Q3 (Oct-Dec 2025) saw sequential revenue declines as the industry digested a record equipment shipment cycle. But management raised full-year guidance to JPY 2,380-2,410B with the second half guided to a record JPY 1,100B+ in sales. TEL projects the WFE (wafer fab equipment) market will grow 15-20%+ in calendar year 2026, driven by AI server chip demand, leading-edge logic node transitions, and sharp increases in both HBM and commodity DRAM investment. Equipment for advanced AI-related chips is expected to reach ~40% of TEL's total sales by FY2026.
Supply Chain Dependencies
Upstream Suppliers
The Catch
TEL is a cyclical business dressed in structural clothing. FY2025 was a record; FY2026 is guided slightly below it. The coater/developer franchise is genuinely irreplaceable, but it is roughly 25-30% of total revenue — the rest of TEL's business (etch, deposition, cleaning) faces real competition from Applied Materials and Lam Research, both of which are larger in their respective segments. China at 34-38% of revenue is the single biggest risk: a further U.S. export control tightening could remove JPY 200-400B of annual revenue with no substitute customer in the near term. The stock at ~35x earnings prices in a smooth upcycle — any combination of WFE disappointment, China shock, or yen strength would compress the multiple before the earnings even decline. And unlike ASML, which has a genuine monopoly across its entire product line, TEL's monopoly is concentrated in one segment while the rest of the portfolio competes in a three-way oligopoly.
If They Win
If the WFE market enters a sustained AI-driven supercycle — 15-20% annual growth for 3-5 years — and TEL holds its coater/developer monopoly through the 2nm and angstrom-era node transitions, the company becomes the process backbone of every advanced fab built in the 2020s and 2030s. Revenue compounds to JPY 3T+ by FY2028. The AI-related revenue mix permanently shifts above 40%, making TEL less cyclical than its history suggests. The coater/developer franchise expands as EUV layer counts increase at each node — more layers means more coater/developer passes per wafer, which means TEL's most monopolistic product grows faster than the overall WFE market. Geographic diversification to US, Japan, and European fabs replaces China revenue at structurally higher margins. TEL becomes the third pillar of semiconductor equipment alongside ASML and Applied Materials — not the biggest, but the one you cannot build a fab without.
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Not financial advice. All scores generated via AI algorithms using public data.