The Chip — Supply Chain Decomposition

for electronic-grade polysilicon crucibles

⚠ CHOKEPOINT[EXTREME] Spruce Pine, NC is a single geographic point of failure: This single mining district in North Carolina produces the ultra-high-purity quartz (≥99.998% SiO₂) used in crucibles for growing semiconductor-grade silicon crystals. Hurricane Helene (2024) temporarily disrupted supply. No viable substitute location exists at scale.

laser medium in DUV/ArF lithography excimer lasers

⚠ CHOKEPOINT[HIGH] Ukraine historically produced ~70% of global neon: Russia-Ukraine conflict disrupted neon supply; prices spiked 500-600% in 2022. Chipmakers diversified since, but Ukraine remains structurally critical. Neon is a byproduct of steel production — you can't just "mine more."

for damascene interconnects, PCB traces, CoWoS RDL, bonding

for MLCCs, wire bonding, catalytic processes

⚠ CHOKEPOINT[HIGH] Russia produces ~40% of global palladium: Sanctions risk. Palladium is used in every MLCC (multilayer ceramic capacitor) on every AI server board. Substitution with gold is partial but costlier.

for via-fill plugs in middle-of-line interconnects (WF₆ precursor)

⚠ CHOKEPOINT[CRITICAL] China controls ~85% of global tungsten: WF₆ (tungsten hexafluoride) is used in every advanced chip for via-fill deposition. Export controls or restrictions would directly halt all advanced fab operations.

for HF etch chemicals and ArF lithography lens optics

⚠ CHOKEPOINT[HIGH] China produces ~65% of global fluorspar: Feedstock for hydrofluoric acid (HF) — used in wet etch, cleans, and buffered oxide etch at every fab. Also required for ultra-pure CaF₂ optical elements in ASML ArF immersion lenses.

for CMP slurries, gate dielectrics, magnets in equipment motors

⚠ CHOKEPOINT[EXTREME] China controls ~60% of RE mining, ~85% of processing: CeO₂ (cerium oxide) is the primary abrasive in CMP slurries. HfO₂ and La₂O₃ are the gate dielectric materials in every advanced HKMG transistor. China's 2023-2025 export controls on gallium, germanium, and antimony demonstrated willingness to weaponize these supply chains. MP Materials and Lynas are the only meaningful Western alternatives.

for Ta capacitors and ALD barrier layers in Cu interconnects

high-purity bonding wire and flip-chip bump metallurgy

⚠ CHOKEPOINT[HIGH] Xinjiang polysilicon UFLPA compliance risk: ~35-40% of global polysilicon comes from Xinjiang (Daqo, GCL-Poly). US Uyghur Forced Labor Prevention Act creates import/compliance risks for the entire solar AND semiconductor polysilicon chain.

💡 INSIGHTToll-Road Business at the Fab Gate: Linde, Air Products, and Air Liquide (all three now in our universe) supply UHP gases on-site at fab campuses under 15-20 year contracts. Once installed, switching costs are astronomical. These are essentially toll-road businesses embedded in semiconductor manufacturing infrastructure.

chemically amplified resists for all lithography nodes

⚠ CHOKEPOINT[EXTREME] Three Japanese companies control ~90% of EUV photoresist: JSR + TOK + Shin-Etsu. Every sub-5nm chip on Earth — every NVIDIA GPU, every Apple M-series, every AMD Instinct — depends on Japanese photoresist. JSR was taken private by the Japanese government (INCJ) in 2023, making this a strategic national asset. TOK (TOKIF) is now in our universe.

planarization consumables used at every metal layer

metalorganic sources for gate dielectrics, barriers, and high-k layers

⚠ CHOKEPOINT[HIGH] ALD precursors for HfO₂ gates are highly specialized: Only a handful of companies (Merck KGaA, SK Trichem, Entegris) produce semiconductor-grade TEMAH, TDMAT, TMA precursors. These are the chemical ingredients for every high-k metal gate transistor in existence.

millions of liters per day consumed in every fab for wafer cleaning

⚠ CHOKEPOINT[MODERATE] UPW is a critical fab utility with 2–3 provider concentration: A 300mm fab consumes 5-10 million liters of ultra-pure water per day. Kurita and Veolia UPW systems are embedded in fab infrastructure — replacing an installed system requires significant planned downtime.

high-frequency and high-performance substrate materials

⚠ CHOKEPOINT[HIGH] Nitto Denko process tapes are consumed in every packaging flow: Dicing tape and back-grinding tape are mundane but mission-critical consumables. Every chip in the world passes through a Nitto Denko (or Furukawa) tape step at packaging. >50% market share creates real concentration.

the substrate for all leading-edge logic

⚠ CHOKEPOINT[EXTREME] Japan controls ~55% of global 300mm wafers; zero US producers: Shin-Etsu and Sumco (both now in our universe) together supply >55% of global wafer capacity. New capacity takes 3+ years to build. Every AI chip begins life on a Japanese or Taiwanese wafer — there is no US-headquartered 300mm silicon wafer manufacturer of scale.

circuit patterns and blank substrates for lithography

⚠ CHOKEPOINT[HIGH] EUV mask blanks from Hoya + AGC (both Japanese) are near-sole-source: EUV masks use special Ta-based absorbers on ultra-flat quartz substrates. The electron-beam mask writers are a near-monopoly of NuFlare (Toshiba) and IMS Nanofabrication (Austria, TSMC-owned). Lasertec (LSRCY) provides the sole EUV mask blank inspection tool.

the organic dielectric base in every GPU and CPU package

⚠ CHOKEPOINT[EXTREME] IC substrate is the #1 GPU production constraint: Ibiden, Shinko, and AT&S form a three-company oligopoly controlling the entire IC substrate supply for AI accelerators. NVIDIA cited substrate supply (Ibiden) as the primary H100 production constraint in 2023. New substrate capacity takes 3-5 years to build. Ajinomoto ABF film (sole source) sits one layer further upstream.

💡 INSIGHTAT&S is the only Western-domiciled substrate company of scale — investing €2B+ in Leoben, Austria to reduce Japan concentration. Intel awarded AT&S major contracts explicitly to de-risk Ibiden/Shinko dependency.

enabling heterogeneous chiplet integration at advanced packaging

💡 INSIGHTCoWoS is THE Bottleneck: TSMC CoWoS capacity gated the entire H100/B100 ramp in 2023-2024. Blackwell (GB200) uses 2-reticle CoWoS-L panels — doubling silicon area per unit. This halves effective wafer throughput per GPU, making CoWoS the #1 constraint on AI infrastructure scaling even when TSMC has ample logic wafer capacity.

protecting and bonding advanced packages

13.5nm extreme ultraviolet scanners — the most complex machines ever made

⚠ CHOKEPOINT[EXTREME] ASML is the ONLY company in the world that makes EUV scanners: Each tool costs $350M+ (High-NA: $400M+) with ~100,000 parts. Carl Zeiss (private) is sole source for the EUV optical column. Dutch/US export controls have blocked EUV to China. This is the most consequential single-company dependency in all of technology.

defect inspection of EUV mask blanks — a prerequisite for every EUV wafer

⚠ CHOKEPOINT[EXTREME] Lasertec is the only company with EUV mask inspection tools: No alternative exists at the required sensitivity level. Every chip manufactured on EUV nodes — all NVIDIA, AMD, Apple, Qualcomm chips at 5nm and below — depends on Lasertec-cleared mask blanks. A single Japanese company is an unrecognized chokepoint immediately upstream of ASML.

plasma etch and atomic layer etch for pattern transfer

building up thin film layers — every layer in every chip

compound semiconductor and specialty layer growth

💡 INSIGHTGaN and SiC epitaxial equipment is the upstream enabler for next-gen power semiconductors. As AI data centers shift to 48V/400V power architectures, demand for GaN FETs and SiC MOSFETs explodes — and every one of those devices starts with a Veeco or AIXTRON MOCVD step.

measuring, inspecting, and testing at every stage

AMHS, cryogenic storage, wafer transport systems

targeted process steps in fab flow

final integration and packaging of chiplets

⚠ CHOKEPOINT[HIGH] BESI is sole supplier of hybrid bonding equipment at volume: SK Hynix placed landmark March 2026 order signaling transition from TCB to hybrid bonding for HBM4. Hybrid bonding enables 10x interconnect density improvement. BESI's monopoly at this technology transition is a structural supply chokepoint.

cutting wafers into individual dies — happens at every packaging facility

⚠ CHOKEPOINT[HIGH] DISCO Corp has near-monopoly on dicing saws: Every wafer on Earth gets diced into individual dies by a DISCO saw or grinder. ~80% market share with no credible Western alternative. DISCO (DISIY) is now in our universe.

💡 INSIGHTThe Most Valuable Chip on Earth: NVIDIA designs on ARM ISA, fabbed at TSMC N4/N3, packaged in CoWoS-L with HBM3E from SK Hynix/Micron. GB200 NVL72 = 72 GPUs per rack at 140kW. Rubin Ultra (2026) pushes to 600kW/rack. Every company in L01-L05 exists, ultimately, to make this chip possible.

💡 INSIGHTCustom Silicon Surge: Google (TPU), Amazon (Trainium), Microsoft (Maia), Meta (MTIA) are all designing custom AI chips — mostly through AVGO and MRVL. This diversifies away from NVIDIA but concentrates further on TSMC N3/N2.

💡 INSIGHTPCIe Gen 6 (128 GT/s) doubles GPU-to-NIC bandwidth by 2026, enabling 800G NICs to saturate PCIe. Astera Labs and Credo are positioned as connectivity glue for GPU-dense rack architectures — critical to the NVLink/Infiniband fabric build-out.

💡 INSIGHTEvery AI server rack also contains dozens of non-GPU chips: Lattice FPGAs handle secure boot and BMC; Qualcomm Snapdragon handles edge inference. The AI chip ecosystem is broader than NVIDIA GPUs alone.

💡 INSIGHTSpecialty foundries serve markets TSMC won't touch: Tower Semiconductor's SiGe BiCMOS (for ADI, TXN radar/sensing chips), RF SOI (for Qorvo, Skyworks front-ends), and imaging sensor processes are irreplaceable. Intel's failed $5.4B Tower acquisition validated Tower's strategic value.

the design software and intelligence layer enabling all chip design

💡 INSIGHTThe EDA duopoly (SNPS + CDNS) is foundational — every chip company in the world pays them per seat per year. ARM's royalty model means every chip shipped generates recurring IP revenue. Synopsys' Ansys acquisition (pending) would create the first combined chip design + thermal simulation platform.